1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and more particularly to an electrically programmable and erasable nonvolatile semiconductor memory device (hereinafter referred to as a "flash memory") including stacked gate type memory cells (memory transistors).
2. Description of the Background Art
The electrically programmable and erasable flash memory is traditionally well known. This flash memory has a large number of memory transistors for storing data. FIG. 5 shows a cross sectional structure of a general stacked gate type memory transistor 11 formed within a conventional flash memory.
Referring to FIG. 5, drain and source regions 4 and 5 are formed spaced apart at a surface of a p well region 3. The drain and source regions 4 and 5 in this case include an n type impurity of high concentration. On a surface of p well region 3 between drain and source regions 4 and 5, an insulating film (tunnel insulating film) 7 including an extremely thin oxide film, for example, is formed to a thickness of approximately 100 .ANG.. A floating gate 8 is formed on this tunnel insulating film 7, and a control gate (word line) 10 is formed on this floating gate 8 with an interlayer insulating film 9 therebetween. Thus, memory transistor 11 has a double gate structure. The above-described p well region 3 may be replaced by a p type semiconductor substrate.
Memory transistor 11 having the above structure is kept in an erased state or a programmed state. Here, general definitions of erasing and programming of a flash memory will be described. Erasing collectively changes threshold voltages of a plurality of memory transistors 11 to one prescribed state, while programming changes a threshold voltage of a selected memory transistor 11 to another prescribed state. Specifically, the above erasing or programming is performed depending on whether electrons are accumulated in floating gate 8 shown in FIG. 5 or emitted from floating gate 8.
Among flash memories having memory transistors 11 as described above, the one called a DINOR (DIvided bit-line NOR) type flash memory is disclosed in IEICE TRANS. ELECTRON., VOL. E77-C, NO.8 AUGUST 1994, PP.1279.about.1286.
The above-described DINOR type flash memory is in the erased state when electrons are accumulated in floating gate 8 and it is in the programmed state when electrons are drawn out of floating gate 8.
FIG. 6 shows the erased and programmed states of memory transistor 11 in the DINOR type flash memory. Referring to FIG. 6, in the erased state in which electrons are injected into floating gate 8, threshold voltage of memory transistor 11 becomes relatively high. Therefore, current (sense current) of not less than a given value will not flow between drain 4 and source 5 if control gate voltage does not exceed Vg1 as shown in FIG. 6. This is because positive voltage is canceled by a negative charge of electrons accumulated in floating gate 8. Such an erased state corresponds to "1" in FIG. 6. Since electrons accumulated in floating gate 8 do not disappear almost permanently if left as they are, data stored in the gate will also be retained almost forever.
On the other hand, in the programmed state in which electrons are emitted from floating gate 8, the threshold voltage of memory transistor 11 becomes relatively low.
This state corresponds to "0" in FIG. 6. Current (sense current) of not less than the given value will flow between drain 4 and source 5 because the control gate voltage exceeds Vg0.
By sensing the two states above (erased or programmed states), it is possible to read data stored in memory transistor 11.
Next, program and erase operations of the above DINOR type flash memory will be described in more detail with respect to FIGS. 7A and 7B.
Referring first to FIG. 7A, in the program operation, drain 4 is supplied with a write voltage (positive high voltage) Vw (approximately 6 V in general), control gate 10 is supplied with a negative high voltage -Vpp (approximately -10 v), and source 5 is kept open. Therefore, electrons are drawn out of floating gate 8 into drain 4 through an overlapped region of drain 4 and floating gate 8 because of the FN tunnel phenomenon. As a result, the threshold voltage of memory transistor 11 is lowered.
In the erase operation, as shown in FIG. 7B, drain 4 is kept in a floating state, source 5 and p well region 3 are supplied with the negative high voltage -Vpp, and control gate 10 is supplied with a positive high voltage +Vpp. Therefore, a high electric field is applied to a tunnel insulating film 7, and electrons are injected into floating gate 8 from p well region 3 (semiconductor substrate) due to the tunnel phenomenon. As a result, the threshold voltage of memory transistor 11 is raised.
By supplying the above-described voltages to memory transistor 11, memory transistor 11 is shifted to the erased or programmed state and data is programmed or erased. However, the erase operation of the DINOR type flash memory is accompanied by such problems as described below. The problems will be described with respect to FIGS. 8 and 9.
FIG. 8 is a block diagram showing circuits related to the erase operation of a conventional DINOR type flash memory. On a main surface of a semiconductor substrate, a plurality of p well regions 3a are formed, each of which is connected to a well driver 60, a well decoder 71, and a well power supply 50. Well driver 60 supplies a prescribed voltage to p well region 3a, well decoder 71 selects a prescribed p well region 3a, and well power supply 50 generates a prescribed voltage which is supplied to p well region 3a.
A plurality of erase blocks 26 are arranged within a p well region 3a. A plurality of memory transistors 11 constitute these erase blocks 26 for each of which collective erasing is performed. A source line (not shown) connected to sources 5 of memory transistors 11 in each erase block 26 is formed, and it is connected to a source line driver 61. Source line driver 61 supplies a prescribed voltage to the source line and it is connected to a block decoder 70 and a source power supply 51. Block decoder 70 is provided corresponding to each p well region 3a and it selects a prescribed erase block 26 in each p well region 3a. Source power supply 51 generates a prescribed voltage which is applied to the source line.
As described above, a plurality of erase blocks 26 are arranged in a p well region 3a in the conventional flash memory, causing problems in the erase operation. The problems will be described with respect to FIG. 9, which is an illustration showing the erase operation of the conventional flash memory.
Since the erase operation is conducted one by one of the erase blocks 26, during erasing, erase block 26 which is selected (selected erase block) coexists with erase block 26 which is not selected (non-selected erase block) on the same p well region 3a as shown in FIG. 9.
During erasing, -Vpp is supplied to p well region 3a. Simultaneously, a control gate 10a of a memory transistor 11a within the selected erase block is supplied with +Vpp, its drain 4a is set to an open state, and its source 5a is supplied with -Vpp. Meanwhile, a control gate of a memory transistor 11b within the non-selected erase block is grounded, its drain 4b is set to the open state, and its source 5b is supplied with -1/2Vpp as an erase inhibiting voltage.
Since memory transistor 11b in the non-selected erase block and memory transistor 11a in the selected erase block are formed on the same p well region 3a, the emission of electrons from floating gate 8b can not be inhibited perfectly even if the erase inhibiting voltage -1/2Vpp is supplied to source 5b of memory transistor 11b in the non-selected erase block. In other words, a small amount of electrons is drawn out of floating gate 8b.
Therefore, some erase blocks 26 may be falsely erased when a large number of erase blocks are arranged within the same p well region 3a or when data is rewritten many times. Such phenomenon is referred to as a well disturbance in this specification. This well disturbance becomes more serious as flash memories come to have larger storage capacity.